This invention relates generally to semiconductor product design, and more particularly, to yield optimization of design library elements at a library element level or at a product level formed from multiple library element types.
Many semiconductor products, particularly application specific integrated circuits (ASICs), are formed by combining pre-designed units (i.e., integrated circuit library elements) that are organized by circuit type (e.g., memories, logic devices, core devices, etc.). Each library element includes a set of integrated circuit devices that are wired together in order to perform a specific function. In addition, each library element must comply with semiconductor technology layout requirements such as line width, line-to-line space, overlap, etc., so that the sensitivity of the library element to various manufacturing processes can be accounted for when the library element is used in an integrated circuit product and manufacturing processes that fabricate the product. These semiconductor technology layout requirements can generally be classified as required rules and preferred rules. Required rules specify the requirements that must be complied with to satisfy design specifications for release of a product containing such a design, while preferred rules specify rules that if complied with will lead to a better yield of the product. The preferred rules for these library elements will vary when used to form a memory, a logic device, or some other complex device.
Typically, a yield checking tool is used in the design process of a semiconductor product to determine if the design satisfies the required level of compliance to preferred rules. The preferred rules are generally specified in terms of a threshold value and incorporated in a set of rules called a yield checking deck. For example, if a required rule states that an analog component used in a design must meet a threshold of at least 80%, then this value would be the threshold value that needs to be satisfied. In this manner, if a library element selected for the design has a 75% threshold, then the yield checking tool would note that this library element does not satisfy the required rule, leading the designer to find another element for the design. Currently available yield checking tools typically assign one threshold to one library element. These yield checking tools do not take into account that each library element can have different types of implementations of the logic embodied by the element. For example, the different types of library elements for a library element type can vary by area and speed. Because these yield checking tools typically assign one threshold to one library element, these tools cannot apply multiple thresholds to a library element with multiple thresholds. Typically, in these instances, a semiconductor designer will have to manually work their way through the design, checking library elements having multiple thresholds to ascertain whether required design rules have been met.